In a non-volatile memory, such as a flash memory, a transistor which constitutes a memory cell has a floating gate or an insulating film which is called a charge storage layer. Data is stored by accumulating electric charges in the charge storage layer, which is based on a silicon-oxide-nitride-oxide-silicon (SONOS) structure.
U.S. Pat. No. 6,011,725 discloses an exemplary SONOS flash memory based on a virtual ground memory, which is operated by switching between a source and a drain. FIG. 1 is a top view of such a flash memory. In a semiconductor substrate 10, a bit line 12 composed of a diffusion layer is provided. The bit line 12 is extended in a lengthwise direction of FIG. 1. A word line 22 is extended in a widthwise direction. The bit line 12 and the word line 22 are respectively coupled with metal plugs 28 and 26 to connect with interconnection layers.
FIGS. 2(a) through 2(d) are cross-sectional views taken along line A-A in FIG. 1. In a P-type semiconductor substrate 10, the bit line 12 doubles as a source and a drain. An ONO film 20 is then formed on the semiconductor substrate 10. The ONO film 20 includes a tunnel oxide film 14 composed of an oxide silicon film, a trapping layer 16 composed of a nitride silicon film and a top oxide film 18 composed of an oxide silicon film. The word line 22 (e.g., polysilicon) is formed on the ONO film 20. The region of the semiconductor substrate 10 between the bit lines 12 is a channel, and the word line 22 on the channel is a gate electrode 22a. 
Electric charges can be accumulated in two charge storage regions of C1 and C2 in the trapping layer 16 above the regions adjacent to the bit lines 12. FIG. 2(a) shows the state of electric charges being accumulated in the charge storage regions of C1 and C2. FIG. 2(b) and FIG. 2(c) respectively show electric charges being accumulated only in C2 located on the right side and in C1 located on the left. FIG. 2(d) shows no electric charge accumulated on either side of the charge storage regions.
The accumulation of electric charges to the trapping layer is made, if the gate electrode 22a is kept at a positive voltage and the trapping layer 16 is infused with high energy electrons energized by another voltage applied between the bit lines 12. Meanwhile, the erasure of electric charges in the trapping layer 16 is made, if the gate electrode 22a is kept at a negative voltage and the trapping layer 16 is infused with holes (e.g., of electrons and holes ionized by high energy electrons) energized by another voltage applied between the bit lines 12. By switching between the source and drain, electric charges at the right and left side of the charge storage regions can be accumulated and erased.
In a non-volatile memory having a charge storage layer, there have been cases of electric charges being accumulated in the charge storage layer during manufacturing. Electric charges may be accumulated and erased when the trapping layer 16 is infused with high energy electrons and holes between the bit lines 12 during the manufacturing of a memory device.
FIG. 3 is a cross-sectional view corresponding to a view along line B-B in FIG. 1 showing how electric charges accumulating in a charge storage layer during the manufacturing of the memory device. During the manufacturing, plasma 60 formed in the process of dry etching or plasma to plasma chemical vapor deposition (CVD) results as electric charges 62. The electric charges 62 then electrify an interconnection layer 30, the metal plug 26 and the word line 22. As the electric charges 62 try to flow from the word line 22 to the semiconductor substrate 10 via the ONO film 20, the electric charges 62 are accumulated in the trapping layer 16. The electric charges 62 may remain there even after the completion of the manufacturing stage.
The unintended trapping becomes problematic when the electric charges 62 remain in the vicinity of the center of a semiconductor substrate 10 between the bit lines 12 since the electric charges cannot be easily erased during the normal operation of the memory.